1. Field of the Invention
The present invention relates to a solid-image-pickup device configured to convert an incident-light amount into an electric signal by using a plurality of pixels arranged in matrix form, an image-pickup device, and a method of driving the solid-image-pickup device.
2. Description of the Related Art
A complementary-metal-oxide-semiconductor (CMOS) image sensor on which a known series/parallel analog-to-digital converter (hereinafter abbreviated as an ADC) is mounted is disclosed in “W. Yang et al., “An Integrated 800×600 CMOS Image System,” ISSCC Digest of Technical Papers, pp. 304-305, February, 1999”. FIG. 7 is a block diagram illustrating the configuration of a CMOS image sensor on which the known series/parallel ADC is mounted. Namely, unit pixels 12 including a photodiode and an in-pixel amplifier are arranged in matrix form so that a pixel array 11 is formed.
The ADC includes a comparator 13 configured to compare a reference voltage RAMP generated from a digital-to-analog converter (hereinafter abbreviated as a DAC) 19 to analog signals obtained from the unit pixels 12 for each of row lines H0, H1, and so forth via column lines V0, V1, and so forth, and a memory device 51 storing data on a count result obtained by a counter 52 configured to count a comparison time. The ADC includes an n-bit-digital-signal-conversion function. The comparator 13 and the memory device 51 are arranged for each of the column lines V0, V1, and so forth so that a series/parallel-ADC block 54 is formed.
A horizontal-output line 55 includes a horizontal-output line having a width of 2n bits and the 2n sense circuits corresponding to output lines, a subtraction circuit 53 and an output circuit. Further, a timing-control circuit 20 configured to generate an internal-clock signal, a row-scanning circuit 18 configured to control the row address and/or row scanning, and a column-scanning circuit 17 configured to control the column address and/or column scanning are arranged, as a control circuit used to read signals output from the pixel array 11 in sequence.
Operations of the above-described known CMOS image sensor will be described with reference to a timing chart of FIG. 8 and the block diagram of FIG. 7. After electric signals are read from the unit pixels 12 provided on an arbitrary row Hx to column lines V0, V1, and so forth for the first time with stability, the DAC 19 inputs a step-like waveform changing with time to a RAMP, as a reference voltage, and the comparator 13 compares the reference voltage to the voltage of the arbitrary column line Vx. At the same time as when the step-like waveform is inputted to the RAMP, the counter 52 performs the first counting.
When the voltage of the RAMP is equivalent to that of the arbitrary column line Vx, an output of the comparator 13 is inverted. At the same time, data on the count value corresponding to the comparison period is stored in the memory device 51. While the first reading is performed, reset components ΔV of the unit pixels 12 are read. Each of the reset components ΔV includes a noise, as an offset component, where the noises vary with the unit pixels 12.
However, since the variations in the noises of the reset components ΔV are usually insignificant and the reset level is common to all of the pixels 12, the value of an output of the arbitrary column line Vx is almost known. Subsequently, the comparison period can be reduced by adjusting the RAMP voltage when the first reading of the reset components ΔV is performed. According to the above-described known example, therefore, a comparison between the reset components ΔV is made over the counting period (128 clock signals) corresponding to 7 bits.
At the second-reading time, the signal components corresponding to an incident-light amount of each of the unit pixels 12 are read in addition to the reset components ΔV, and the same operations as those performed for the first reading are performed. That is to say, after electric signals are read from the unit pixels 12 provided on the arbitrary row Hx to the column lines V0, V1, and so forth for the second time with stability, the DAC 19 inputs the step-like waveform changing with time to the RAMP, as the reference voltage, and the comparator 13 compares the reference voltage to the voltage of the arbitrary column line Vx.
At the same time as when the step-like waveform is inputted to the RAMP, the counter 52 performs the second counting. When the voltage of the RAMP is equivalent to that of the arbitrary column line Vx, an output of the comparator 13 is inverted. At the same time, data on the count value corresponding to the comparison period is stored in the memory device 51. At that time, data on the value of the first counting and that on the value of the second counting are stored in the memory device 51 at different locations.
After the above-described AD-conversion period is over, the column-scanning circuit 17 transmits n-bit digital signals that are obtained by the first counting and that are stored in the memory device 51, and n-bit digital signals that are obtained by the second counting and that are stored in the memory device 51 to the subtraction circuit 53 via 2n horizontal-output lines 55 so that the n-bit digital signals obtained by the first counting are subtracted from the n-bit digital signals obtained by the second counting in sequence and externally transmitted. After that, the above-described operations are performed for each of rows in sequence, so that a two-dimensional image is generated.